@context
dict | @type
string | name
string | description
string | license
string | version
string | datePublished
timestamp[s] | url
string | creator
dict | citeAs
string | conformsTo
string | distribution
list | recordSet
list |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
{
"@language": "en",
"@vocab": "https://schema.org/",
"citeAs": "cr:citeAs",
"column": "cr:column",
"conformsTo": "dct:conformsTo",
"cr": "http://mlcommons.org/croissant/",
"rai": "http://mlcommons.org/croissant/RAI/",
"data": {
"@id": "cr:data",
"@type": "@json"
},
"dataType": {
"@id": "cr:dataType",
"@type": "@vocab"
},
"dct": "http://purl.org/dc/terms/",
"examples": {
"@id": "cr:examples",
"@type": "@json"
},
"extract": "cr:extract",
"field": "cr:field",
"fileProperty": "cr:fileProperty",
"fileObject": "cr:fileObject",
"fileSet": "cr:fileSet",
"format": "cr:format",
"includes": "cr:includes",
"isLiveDataset": "cr:isLiveDataset",
"jsonPath": "cr:jsonPath",
"key": "cr:key",
"md5": "cr:md5",
"parentField": "cr:parentField",
"path": "cr:path",
"recordSet": "cr:recordSet",
"references": "cr:references",
"regex": "cr:regex",
"repeated": "cr:repeated",
"replace": "cr:replace",
"sc": "https://schema.org/",
"separator": "cr:separator",
"source": "cr:source",
"subField": "cr:subField",
"transform": "cr:transform"
}
|
sc:Dataset
|
ChiPBench-D
|
A dataset of digital design with standard DEF/LEF/Liberty/Verilog/SDC files, intended for use in EDA placement benchmarks.
|
https://opensource.org/licenses/MIT
|
1.0
| 2025-05-08T00:00:00
|
https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D
|
{
"@type": "sc:Person",
"name": "MIRA-Lab"
}
|
ChiPBench-D
|
http://mlcommons.org/croissant/1.0
|
[
{
"@type": "cr:FileObject",
"@id": "repo",
"name": "ChiPBench-D Repository",
"description": "Git repository containing all ChiPBench-D design files",
"contentUrl": "https://huggingface.co/datasets/MIRA-Lab/ChiPBench-D",
"encodingFormat": "git+https",
"sha256": "main",
"containedIn": null,
"includes": null
},
{
"@type": "cr:FileSet",
"@id": "verilog-files",
"name": "Verilog Files",
"description": "Verilog Files",
"contentUrl": null,
"encodingFormat": "text/plain",
"sha256": null,
"containedIn": {
"@id": "repo"
},
"includes": "data/*/*.v"
},
{
"@type": "cr:FileSet",
"@id": "sdc-files",
"name": "SDC Files",
"description": "LEF Files",
"contentUrl": null,
"encodingFormat": "text/plain",
"sha256": null,
"containedIn": {
"@id": "repo"
},
"includes": "data/*/*.sdc"
},
{
"@type": "cr:FileSet",
"@id": "lef-files",
"name": "LEF Files",
"description": "LEF Files",
"contentUrl": null,
"encodingFormat": "text/plain",
"sha256": null,
"containedIn": {
"@id": "repo"
},
"includes": "data/*/lef/*.lef"
},
{
"@type": "cr:FileSet",
"@id": "lib-files",
"name": "Liberty Files",
"description": "Liberty Files",
"contentUrl": null,
"encodingFormat": "text/plain",
"sha256": null,
"containedIn": {
"@id": "repo"
},
"includes": "data/*/lib/*.lib"
},
{
"@type": "cr:FileSet",
"@id": "def-files",
"name": "DEF Files",
"description": "DEF Files",
"contentUrl": null,
"encodingFormat": "text/plain",
"sha256": null,
"containedIn": {
"@id": "repo"
},
"includes": "data/*/def/*.def"
}
] |
[
{
"@type": "cr:RecordSet",
"@id": "verilog_file",
"name": "verilog_file",
"description": "Records of Verilog design files",
"field": [
{
"@type": "cr:Field",
"@id": "verilog_file/design_name",
"name": "design_name",
"dataType": "sc:Text",
"description": "Design name extracted from Verilog file path",
"source": {
"fileSet": {
"@id": "verilog-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": {
"regex": "data/([^/]+)/[^/]+\\.v$"
}
}
},
{
"@type": "cr:Field",
"@id": "verilog_file/verilog_path",
"name": "verilog_path",
"dataType": "sc:Text",
"description": "Full path of the Verilog file",
"source": {
"fileSet": {
"@id": "verilog-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": null
}
},
{
"@type": "cr:Field",
"@id": "verilog_file/verilog_content",
"name": "verilog_content",
"dataType": "sc:Text",
"description": "Content of the Verilog design file",
"source": {
"fileSet": {
"@id": "verilog-files"
},
"extract": {
"fileProperty": "content"
},
"transform": null
}
}
]
},
{
"@type": "cr:RecordSet",
"@id": "sdc_file",
"name": "sdc_file",
"description": "Records of SDC timing constraint files",
"field": [
{
"@type": "cr:Field",
"@id": "sdc_file/design_name",
"name": "design_name",
"dataType": "sc:Text",
"description": "Design name extracted from SDC file path",
"source": {
"fileSet": {
"@id": "sdc-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": {
"regex": "data/([^/]+)/[^/]+\\.sdc$"
}
}
},
{
"@type": "cr:Field",
"@id": "sdc_file/sdc_path",
"name": "sdc_path",
"dataType": "sc:Text",
"description": "Full path of the SDC file",
"source": {
"fileSet": {
"@id": "sdc-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": null
}
},
{
"@type": "cr:Field",
"@id": "sdc_file/sdc_content",
"name": "sdc_content",
"dataType": "sc:Text",
"description": "Content of the SDC constraint file",
"source": {
"fileSet": {
"@id": "sdc-files"
},
"extract": {
"fileProperty": "content"
},
"transform": null
}
}
]
},
{
"@type": "cr:RecordSet",
"@id": "lef_file",
"name": "lef_file",
"description": "Records of LEF technology/library files",
"field": [
{
"@type": "cr:Field",
"@id": "lef_file/design_name",
"name": "design_name",
"dataType": "sc:Text",
"description": "Design name extracted from LEF file path",
"source": {
"fileSet": {
"@id": "lef-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": {
"regex": "data\\/([^\\/]+)\\/lef\\/[^\\/]+\\.lef$"
}
}
},
{
"@type": "cr:Field",
"@id": "lef_file/lef_content",
"name": "lef_content",
"dataType": "sc:Text",
"description": "Content of the LEF file",
"source": {
"fileSet": {
"@id": "lef-files"
},
"extract": {
"fileProperty": "content"
},
"transform": null
}
},
{
"@type": "cr:Field",
"@id": "lef_file/lef_paths",
"name": "lef_paths",
"dataType": "sc:Text",
"description": "Full path of the LEF file",
"source": {
"fileSet": {
"@id": "lef-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": null
}
}
]
},
{
"@type": "cr:RecordSet",
"@id": "lib_file",
"name": "lib_file",
"description": "Records of Liberty (.lib) timing files",
"field": [
{
"@type": "cr:Field",
"@id": "lib_file/design_name",
"name": "design_name",
"dataType": "sc:Text",
"description": "Design name extracted from Liberty file path",
"source": {
"fileSet": {
"@id": "lib-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": {
"regex": "data\\/([^\\/]+)\\/lib\\/[^\\/]+\\.lib$"
}
}
},
{
"@type": "cr:Field",
"@id": "lib_file/lib_paths",
"name": "lib_paths",
"dataType": "sc:Text",
"description": "Full path of the Liberty file",
"source": {
"fileSet": {
"@id": "lib-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": null
}
},
{
"@type": "cr:Field",
"@id": "lib_file/lib_content",
"name": "lib_content",
"dataType": "sc:Text",
"description": "Content of the Liberty timing file",
"source": {
"fileSet": {
"@id": "lib-files"
},
"extract": {
"fileProperty": "content"
},
"transform": null
}
}
]
},
{
"@type": "cr:RecordSet",
"@id": "def_file",
"name": "def_file",
"description": "Records of DEF placement/routing files",
"field": [
{
"@type": "cr:Field",
"@id": "def_file/design_name",
"name": "design_name",
"dataType": "sc:Text",
"description": "Design name extracted from DEF file path",
"source": {
"fileSet": {
"@id": "def-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": {
"regex": "data\\/([^\\/]+)\\/def\\/[^\\/]+\\.def$"
}
}
},
{
"@type": "cr:Field",
"@id": "def_file/def_paths",
"name": "def_paths",
"dataType": "sc:Text",
"description": "Full path of the DEF file",
"source": {
"fileSet": {
"@id": "def-files"
},
"extract": {
"fileProperty": "fullpath"
},
"transform": null
}
},
{
"@type": "cr:Field",
"@id": "def_file/def_content",
"name": "def_content",
"dataType": "sc:Text",
"description": "Content of the DEF file",
"source": {
"fileSet": {
"@id": "def-files"
},
"extract": {
"fileProperty": "content"
},
"transform": null
}
}
]
}
] |
ChiPBench-D
ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms
Chip placement is a critical step in the Electronic Design Automation (EDA) workflow, which aims to arrange chip modules on the canvas to optimize the performance, power, and area (PPA) metrics of final designs.
Recent advances show great potential of AI-based algorithms in chip placement.
However, due to the lengthy EDA workflow, evaluations of these algorithms often focus on intermediate surrogate metrics, which are computationally efficient but often misalign with the final end-to-end performance (i.e., the final design PPA).
To address this challenge, we propose to build ChiPBench, a comprehensive benchmark specifically designed to evaluate the effectiveness of AI-based algorithms in final design PPA metrics.
Specifically, we generate a diverse evaluation dataset from 20 circuits across various domains, such as CPUs, GPUs, and NPUs.
We present an end-to-end evaluation workflow for placement stages of the EDA flow.
To evaluate a stage-specific algorithm, the output from the preceding stage serves as its input, and the algorithm's output is reintegrated into the original design flow.
Final PPA metrics provide a comprehensive assessment, avoiding the limitations of isolated stage-specific metrics.
This approach facilitates algorithm optimization by ensuring improvements translate into practical chip design enhancements.
We believe ChiPBench will effectively bridge the gap between academia and industry.
This project represents the dataset part of ChiPBench. The code can be found on GitHub: ChiPBench.
Details
data
data
├── case_name
│ ├── def
│ ├── lef
│ ├── lib
│ ├── case_name.v
│ ├── constraint.sdc
- def: DEF files.
pre_place.def: Floorplan initialization completed; macros and standard cells are not yet placed.macro_placed.def: Macros are fixed in place (placed using OpenROAD's Hier-RTLMP method); standard cells are not yet placed.
- lef: Case-specific LEF files.
- lib: Case-specific LIB files.
- case_name.v: Synthesized netlist files for the case.
- constraint.sdc: Timing constraint files for the case.
Download Using Croissant Format
You only need to download the following files first:
Then run the following commands:
mkdir ChiPBench-D
cp download_dataset.py ChiPBench-D/
cp chipbench_meta_data.json ChiPBench-D/
cd ChiPBench-D/
python3 download_dataset.py
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